Due to a common server has a request of high quality for a supplying of a power supply, especially for some global servers like a bank systems, traffic signal controlling systems that do not permit a fault occurred resulted from a power failure. Therefore, a longer voltage holdup time is required for a server power supply, i.e.: when a power failure is occurred, the output voltage can be maintained a certain time for ensuring data losses being not occurred in the server. A common power supply can not achieve the request due to the voltage holdup time being too shorter.
FIG. 1 shows a schematic diagram of a power supply with variable turns ratio. It employs the method of changing turns ratio to extend the voltage holdup time for achieving the request of the server. In FIG. 1, the capacitor C1 is a bulk capacitor in the DC (direct current) input bus and the transformer T1 is a high frequency transformer. By the DC/DC converter CON, the voltage of the DC input bus is transferred to a high-frequency pulse voltage applied to the primary winding N1 of the transformer T1. A full-wave rectifier is applied to the secondary side of the transformer T1. In view of the function of the circuit, the primary rectifier comprises first secondary windings N21, N22 and first rectifying diodes D1 and D2. The additional rectifier comprises second secondary windings N31, N32 and second rectifying diodes D3 and D4. Switching transistor Q5 is a switch between the two rectifiers and in generally, is a MOSFET. A switch signal is generated by a control circuit CTRL and an input control voltage BV of the control circuit CTRL is equal to voltage Vc1 of the bulk capacitor C1. A common filter circuit of the primary rectifier and the additional rectifier comprises an inductance Lf and a capacitor Cf. When the voltage in input bus is regular, the control circuit CTRL does not generate a switch signal, a gate-voltage of the switching transistor Q5 is low voltage and the switching transistor Q5 turns off. Therefore, only primary rectifier participates in the voltage-transforming in secondary side of the transformer T1. If power cut is happened, the voltage across the capacitor C1 is decreasing until a predetermined voltage Vset (adjustable). When the voltage across the capacitor C1 is equal to the voltage Vset, the control circuit CTRL generates a pulse of switch signal with a certain width and so the switching transistor Q5 turns on. Primary rectifier and the additional rectifier participate in the voltage-transforming in secondary side together. Hence, the output voltage Vo is maintained for a longer time after power cut.
FIG. 2 shows a schematic diagram of voltages when the voltage holdup circuit is working. In FIG. 2, Vc1 is the voltage across the bulk capacitor C1, i.e.: the controlling voltage BV of the control circuit CTRL; Vo is the output voltage of the power supply; Vgs is the voltage of the switch signal, i.e.: the gate-voltage of the switching transistor Q5; and Vset is a predetermined voltage of the control circuit CTRL. When the voltage in input bus is regular (higher than the predetermined voltage Vset), the output voltage maintains in a predetermined output voltage, the switch signal Vgs of the control circuit CTRL is low voltage. Therefore, the switching transistor Q5 turns off and only primary rectifier participates in the voltage-transforming in secondary side. At the time t0, power cut is happened and the voltage Vc1 across the capacitor C1 and the controlling voltage BV of the control circuit CTRL are decreasing. At the time t1, the voltage BV is equal to the predetermined voltage Vset and the switch signal Vgs of the control circuit CTRL is turned into high voltage and maintains for a certain time. Therefore, the switching transistor Q5 turns on and the primary rectifier and the additional rectifier participate in the voltage-transforming in secondary side together. At the time t2, the output voltage of the power supply begins to decrease and the voltage holdup time th is equal to (t2−t0). The switch signal Vgs of the control circuit CTRL must at least maintain high voltage until the time t2.
If the DC/DC converter in the primary side of the transformer T1 is a phase shifted full bridge converter, the relationship between the voltage Vc1 across the capacitor C1 and the output voltage Vo can be written as:Vo=2nVC1D  (1)
Wherein, n is the turns ratio of transformer; and D is the duty cycle of the switching transistor.
The voltage holdup time can be written as:                     th        =                                            1                              P                o                                      ·                          1              2                                ⁢                                                    C                1                            ⁡                              [                                                      V                    t0                    2                                    -                                                            (                                                                        V                          o                                                                          2                          ⁢                                                      nD                            max                                                                                              )                                        2                                                  ]                                      ·            η                                              (        2        )            
Wherein, P0 is the output power of the power supply; C1 is the capacitance of capacitor C1; Vt0 is the value of the voltage across capacitor C1 at the time t0; Dmax is the maximum duty cycle; and η is the transforming efficiency of the transformer.
When the additional rectifier participates in the voltage-transforming in secondary side, the turns ratio of transformer T1 is transferred from n2/n1 to (n2+n3)/n1, wherein the turns of the primary winding is n1, the turns of the first secondary windings N21 and N22 is n2, and the turns of the second secondary windings N31 and N32 is n3. According to Eq. (2), if other parameters is constant, the minimum capacitor voltage Vo/2nDmax becomes smaller due to the ratio turns n becoming larger, and so the voltage holdup time th also becomes longer.
FIG. 3A and FIG. 3B show measured voltage waveforms under output voltage being 12V with voltage holdup circuit. The voltage waveforms in FIG. 3A are measured without the additional rectifier, wherein Vc1 is the voltage across capacitor C1, Vo is the output voltage, Vac is the voltage of the alternating current (AC) voltage, and the voltage holdup time is 11.4 ms. The voltage waveforms in FIG. 3B are measured with the additional rectifier, wherein Vgs is the gate-voltage of the switching transistor Q5, and the voltage holdup time is extended to 22.0 ms.
Due to the additional rectifier participating in the voltage-transforming during the voltage holdup time, a required voltage endurance and a required current endurance of the additional rectifier are little and the additional rectifier is almost without a problem of diffusing heat. Therefore, the dimension of the additional rectifier can be small. However, the additional rectifier brings another problem of a peak voltage in the output voltage resulted from the additional rectifier participating in the voltage-transforming. FIG. 3B shows that a peak voltage is about 220 mV when a switching operation of the switch is done, i.e.: the additional rectifier participating in the voltage-transforming.
The reason that the peak voltage is occurred can be obtained from a analysis of the regulating feature of the converter. As shown in FIG. 4, when the gate-voltage of the switching transistor Q5 is high voltage, the additional rectifier is switched to participate in the voltage-transforming with the primary rectifier. A duty cycle D of transistors in the DC/DC converter can be obtained according to a voltage difference Vd from a voltage regulator being compared with a sawtooth wave Vt. The duty cycle D also is a duty cycle of the output voltage of the transformer (no matter that the duty cycle loss). If the turns ratio of the transformer is n2/n1, the voltage across the capacitor C1 is Vset, and the duty cycle D is Dset at the start of the switching duration. Then, the turns ratio suddenly increases to become (n2+n3)/n1, but the voltage across the capacitor C1 is still Vset, and the duty cycle D is still Dset. Hence, according to Eq. (1), the voltage across the secondary winding of the transformer is instantly increased. However, a regulating rate of the duty cycle D through a feedback network of the power supply is limited by a cutoff frequency and a wire delay thereof. Therefore, after the switching, the voltage regulator still maintains a state, as well as that before switching, for a certain time. Therefore, the duty cycles of the transistor and the voltage across the secondary winding also maintain constant for a certain time after the switching. Hence, the voltage across the secondary winding passes through the filter circuit and a peak voltage is occurred in the output voltage of the power supply during the switching duration.
FIG. 5A and FIG. 5B show the output voltage waveforms during the switching duration. The waveforms are measured under the state that the DC/DC converter is a phase shifted full bridge converter and the output loading is 48V and 5A. The waveforms in FIG. 5B are enlarged from the waveform in FIG. 5A. The channel 2 is the 48V output signal and the channel 3 is the switch signal. The duration of the switch signal must be suitably determined for ensuring that the voltage holdup time is enough long (21 ms, in general). FIG. 5A and FIG. 5B show that a peak voltage is about 320 mV during the switching duration.
In general, the peak voltage of the output voltage is limited to smaller than a certain magnitude, when the additional rectifier is switched to participate with the primary rectifier. However, in those conventional arts, the server power supply is limited by the cutoff frequency and the wire delay and so the problem of the peak voltage is occurred. Hence, the quality of the power supply is lowered and so some unexpected problems will occur.